Apparatus and method for processing sparse data

ABSTRACT

An apparatus and method are described for designing an accelerator for processing sparse data. For example, one embodiment comprises a machine-readable medium having program code stored thereon which, when executed by a processor, causes the processor to perform the operations of: analyzing input graph program code and parameters associated with a target accelerator in view of an accelerator architecture template; responsively mapping the parameters onto the architecture template to implement customizations to the accelerator architecture template; and generating a hardware description representation of the target accelerator based on the determined mapping of the parameters to apply to the accelerator architecture template.

BACKGROUND Field of the Invention

This invention relates generally to the field of computer processors andaccelerators. More particularly, the invention relates to an apparatusand method for processing sparse data.

Description of the Related Art

Graph analytics relies on graph algorithms to extract knowledge aboutthe relationship among data represented as graphs. The proliferation ofgraph data (from sources such as social media) has led to strong demandfor and wide use of graph analytics. As such, being able to do graphanalytics as efficiently as possible is of critical importance.

There are existing graph analytics frameworks, but they are primarilysoftware frameworks (i.e., running on CPUs of GPGPUs). For the limitedgraph frameworks which map graph algorithms to customized hardware,their target hardware accelerator architectures are not based ongeneralized sparse matrix vector multiply. There are existing sparsematrix multiply hardware accelerators, but they do not supportcustomizability to allow mapping of graph algorithms.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained from thefollowing detailed description in conjunction with the followingdrawings, in which:

FIGS. 1A and 1B are block diagrams illustrating a generic vectorfriendly instruction format and instruction templates thereof accordingto embodiments of the invention;

FIG. 2A-D is a block diagram illustrating an exemplary specific vectorfriendly instruction format according to embodiments of the invention;

FIG. 3 is a block diagram of a register architecture according to oneembodiment of the invention; and

FIG. 4A is a block diagram illustrating both an exemplary in-orderfetch, decode, retire pipeline and an exemplary register renaming,out-of-order issue/execution pipeline according to embodiments of theinvention;

FIG. 4B is a block diagram illustrating both an exemplary embodiment ofan in-order fetch, decode, retire core and an exemplary registerrenaming, out-of-order issue/execution architecture core to be includedin a processor according to embodiments of the invention;

FIG. 5A is a block diagram of a single processor core, along with itsconnection to an on-die interconnect network;

FIG. 5B illustrates an expanded view of part of the processor core inFIG. 5A according to embodiments of the invention;

FIG. 6 is a block diagram of a single core processor and a multicoreprocessor with integrated memory controller and graphics according toembodiments of the invention;

FIG. 7 illustrates a block diagram of a system in accordance with oneembodiment of the present invention;

FIG. 8 illustrates a block diagram of a second system in accordance withan embodiment of the present invention;

FIG. 9 illustrates a block diagram of a third system in accordance withan embodiment of the present invention;

FIG. 10 illustrates a block diagram of a system on a chip (SoC) inaccordance with an embodiment of the present invention;

FIG. 11 illustrates a block diagram contrasting the use of a softwareinstruction converter to convert binary instructions in a sourceinstruction set to binary instructions in a target instruction setaccording to embodiments of the invention;

FIG. 12 illustrates an architecture on which embodiments of theinvention may be implemented;

FIG. 13 illustrates one embodiment of an architecture for processingsparse data;

FIG. 14 illustrates different sparse data operations employed in oneembodiment;

FIGS. 15a-c illustrate formats used for matrix data in one embodiment;

FIGS. 16a-c illustrate pseudocode for operations performed in oneembodiment;

FIG. 17 illustrates a processor element architecture in one embodiment;

FIGS. 18a-b illustrates data flow in accordance with one embodiment;

FIGS. 19a-e illustrates graphing data and program code in accordancewith one embodiment;

FIG. 20 illustrates template mapping, validation, and automatic tuningemployed in one embodiment;

FIG. 21 illustrates one embodiment of a data management unit andprocessor element architecture;

FIG. 22 illustrates a method in accordance with one embodiment of theinvention;

FIG. 23a-b illustrate different categories and tuning considerations;and

FIG. 24 illustrates one embodiment of a method in accordance with oneembodiment of the invention.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the embodiments of the invention described below. Itwill be apparent, however, to one skilled in the art that theembodiments of the invention may be practiced without some of thesespecific details. In other instances, well-known structures and devicesare shown in block diagram form to avoid obscuring the underlyingprinciples of the embodiments of the invention.

Exemplary Processor Architectures and Data Types

An instruction set includes one or more instruction formats. A giveninstruction format defines various fields (number of bits, location ofbits) to specify, among other things, the operation to be performed(opcode) and the operand(s) on which that operation is to be performed.Some instruction formats are further broken down though the definitionof instruction templates (or subformats). For example, the instructiontemplates of a given instruction format may be defined to have differentsubsets of the instruction format's fields (the included fields aretypically in the same order, but at least some have different bitpositions because there are less fields included) and/or defined to havea given field interpreted differently. Thus, each instruction of an ISAis expressed using a given instruction format (and, if defined, in agiven one of the instruction templates of that instruction format) andincludes fields for specifying the operation and the operands. Forexample, an exemplary ADD instruction has a specific opcode and aninstruction format that includes an opcode field to specify that opcodeand operand fields to select operands (source1/destination and source2);and an occurrence of this ADD instruction in an instruction stream willhave specific contents in the operand fields that select specificoperands. A set of SIMD extensions referred to the Advanced VectorExtensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX)coding scheme, has been released and/or published (e.g., see Intel® 64and IA-32 Architectures Software Developers Manual, October 2011; andsee Intel® Advanced Vector Extensions Programming Reference, June 2011).

Exemplary Instruction Formats

Embodiments of the instruction(s) described herein may be embodied indifferent formats. Additionally, exemplary systems, architectures, andpipelines are detailed below. Embodiments of the instruction(s) may beexecuted on such systems, architectures, and pipelines, but are notlimited to those detailed.

A. Generic Vector Friendly Instruction Format

A vector friendly instruction format is an instruction format that issuited for vector instructions (e.g., there are certain fields specificto vector operations). While embodiments are described in which bothvector and scalar operations are supported through the vector friendlyinstruction format, alternative embodiments use only vector operationsthe vector friendly instruction format.

FIGS. 1A-1B are block diagrams illustrating a generic vector friendlyinstruction format and instruction templates thereof according toembodiments of the invention. FIG. 1A is a block diagram illustrating ageneric vector friendly instruction format and class A instructiontemplates thereof according to embodiments of the invention; while FIG.1B is a block diagram illustrating the generic vector friendlyinstruction format and class B instruction templates thereof accordingto embodiments of the invention. Specifically, a generic vector friendlyinstruction format 100 for which are defined class A and class Binstruction templates, both of which include no memory access 105instruction templates and memory access 120 instruction templates. Theterm generic in the context of the vector friendly instruction formatrefers to the instruction format not being tied to any specificinstruction set.

While embodiments of the invention will be described in which the vectorfriendly instruction format supports the following: a 64 byte vectoroperand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) dataelement widths (or sizes) (and thus, a 64 byte vector consists of either16 doubleword-size elements or alternatively, 8 quadword-size elements);a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit(1 byte) data element widths (or sizes); a 32 byte vector operand length(or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8bit (1 byte) data element widths (or sizes); and a 16 byte vectoroperand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit(2 byte), or 8 bit (1 byte) data element widths (or sizes); alternativeembodiments may support more, less and/or different vector operand sizes(e.g., 256 byte vector operands) with more, less, or different dataelement widths (e.g., 128 bit (16 byte) data element widths).

The class A instruction templates in FIG. 1A include: 1) within the nomemory access 105 instruction templates there is shown a no memoryaccess, full round control type operation 110 instruction template and ano memory access, data transform type operation 115 instructiontemplate; and 2) within the memory access 120 instruction templatesthere is shown a memory access, temporal 125 instruction template and amemory access, non-temporal 130 instruction template. The class Binstruction templates in FIG. 1B include: 1) within the no memory access105 instruction templates there is shown a no memory access, write maskcontrol, partial round control type operation 112 instruction templateand a no memory access, write mask control, vsize type operation 117instruction template; and 2) within the memory access 120 instructiontemplates there is shown a memory access, write mask control 127instruction template.

The generic vector friendly instruction format 100 includes thefollowing fields listed below in the order illustrated in FIGS. 1A-1B.

Format field 140—a specific value (an instruction format identifiervalue) in this field uniquely identifies the vector friendly instructionformat, and thus occurrences of instructions in the vector friendlyinstruction format in instruction streams. As such, this field isoptional in the sense that it is not needed for an instruction set thathas only the generic vector friendly instruction format.

Base operation field 142—its content distinguishes different baseoperations.

Register index field 144—its content, directly or through addressgeneration, specifies the locations of the source and destinationoperands, be they in registers or in memory. These include a sufficientnumber of bits to select N registers from a P×Q (e.g. 32×512, 16×128,32×1024, 64×1024) register file. While in one embodiment N may be up tothree sources and one destination register, alternative embodiments maysupport more or less sources and destination registers (e.g., maysupport up to two sources where one of these sources also acts as thedestination, may support up to three sources where one of these sourcesalso acts as the destination, may support up to two sources and onedestination).

Modifier field 146—its content distinguishes occurrences of instructionsin the generic vector instruction format that specify memory access fromthose that do not; that is, between no memory access 105 instructiontemplates and memory access 120 instruction templates. Memory accessoperations read and/or write to the memory hierarchy (in some casesspecifying the source and/or destination addresses using values inregisters), while non-memory access operations do not (e.g., the sourceand destinations are registers). While in one embodiment this field alsoselects between three different ways to perform memory addresscalculations, alternative embodiments may support more, less, ordifferent ways to perform memory address calculations.

Augmentation operation field 150—its content distinguishes which one ofa variety of different operations to be performed in addition to thebase operation. This field is context specific. In one embodiment of theinvention, this field is divided into a class field 168, an alpha field152, and a beta field 154. The augmentation operation field 150 allowscommon groups of operations to be performed in a single instructionrather than 2, 3, or 4 instructions.

Scale field 160—its content allows for the scaling of the index field'scontent for memory address generation (e.g., for address generation thatuses 2^(scale)*index+base).

Displacement Field 162A—its content is used as part of memory addressgeneration (e.g., for address generation that uses2^(scale)*index+base+displacement).

Displacement Factor Field 162B (note that the juxtaposition ofdisplacement field 162A directly over displacement factor field 162Bindicates one or the other is used)—its content is used as part ofaddress generation; it specifies a displacement factor that is to bescaled by the size of a memory access (N)—where N is the number of bytesin the memory access (e.g., for address generation that uses2^(scale)*index+base+scaled displacement). Redundant low-order bits areignored and hence, the displacement factor field's content is multipliedby the memory operands total size (N) in order to generate the finaldisplacement to be used in calculating an effective address. The valueof N is determined by the processor hardware at runtime based on thefull opcode field 174 (described later herein) and the data manipulationfield 154C. The displacement field 162A and the displacement factorfield 162B are optional in the sense that they are not used for the nomemory access 105 instruction templates and/or different embodiments mayimplement only one or none of the two.

Data element width field 164—its content distinguishes which one of anumber of data element widths is to be used (in some embodiments for allinstructions; in other embodiments for only some of the instructions).This field is optional in the sense that it is not needed if only onedata element width is supported and/or data element widths are supportedusing some aspect of the opcodes.

Write mask field 170—its content controls, on a per data elementposition basis, whether that data element position in the destinationvector operand reflects the result of the base operation andaugmentation operation. Class A instruction templates supportmerging-writemasking, while class B instruction templates support bothmerging- and zeroing-writemasking. When merging, vector masks allow anyset of elements in the destination to be protected from updates duringthe execution of any operation (specified by the base operation and theaugmentation operation); in other one embodiment, preserving the oldvalue of each element of the destination where the corresponding maskbit has a 0. In contrast, when zeroing vector masks allow any set ofelements in the destination to be zeroed during the execution of anyoperation (specified by the base operation and the augmentationoperation); in one embodiment, an element of the destination is set to 0when the corresponding mask bit has a 0 value. A subset of thisfunctionality is the ability to control the vector length of theoperation being performed (that is, the span of elements being modified,from the first to the last one); however, it is not necessary that theelements that are modified be consecutive. Thus, the write mask field170 allows for partial vector operations, including loads, stores,arithmetic, logical, etc. While embodiments of the invention aredescribed in which the write mask field's 170 content selects one of anumber of write mask registers that contains the write mask to be used(and thus the write mask field's 170 content indirectly identifies thatmasking to be performed), alternative embodiments instead or additionalallow the mask write field's 170 content to directly specify the maskingto be performed.

Immediate field 172—its content allows for the specification of animmediate. This field is optional in the sense that is it not present inan implementation of the generic vector friendly format that does notsupport immediate and it is not present in instructions that do not usean immediate.

Class field 168—its content distinguishes between different classes ofinstructions. With reference to FIGS. 1A-B, the contents of this fieldselect between class A and class B instructions. In FIGS. 1A-B, roundedcorner squares are used to indicate a specific value is present in afield (e.g., class A 168A and class B 168B for the class field 168respectively in FIGS. 1A-B).

Instruction Templates of Class A

In the case of the non-memory access 105 instruction templates of classA, the alpha field 152 is interpreted as an RS field 152A, whose contentdistinguishes which one of the different augmentation operation typesare to be performed (e.g., round 152A.1 and data transform 152A.2 arerespectively specified for the no memory access, round type operation110 and the no memory access, data transform type operation 115instruction templates), while the beta field 154 distinguishes which ofthe operations of the specified type is to be performed. In the nomemory access 105 instruction templates, the scale field 160, thedisplacement field 162A, and the displacement scale filed 162B are notpresent.

No-Memory Access Instruction Templates—Full Round Control Type Operation

In the no memory access full round control type operation 110instruction template, the beta field 154 is interpreted as a roundcontrol field 154A, whose content(s) provide static rounding. While inthe described embodiments of the invention the round control field 154Aincludes a suppress all floating point exceptions (SAE) field 156 and around operation control field 158, alternative embodiments may supportmay encode both these concepts into the same field or only have one orthe other of these concepts/fields (e.g., may have only the roundoperation control field 158).

SAE field 156—its content distinguishes whether or not to disable theexception event reporting; when the SAE field's 156 content indicatessuppression is enabled, a given instruction does not report any kind offloating-point exception flag and does not raise any floating pointexception handler.

Round operation control field 158—its content distinguishes which one ofa group of rounding operations to perform (e.g., Round-up, Round-down,Round-towards-zero and Round-to-nearest). Thus, the round operationcontrol field 158 allows for the changing of the rounding mode on a perinstruction basis. In one embodiment of the invention where a processorincludes a control register for specifying rounding modes, the roundoperation control field's 150 content overrides that register value.

No Memory Access Instruction Templates—Data Transform Type Operation

In the no memory access data transform type operation 115 instructiontemplate, the beta field 154 is interpreted as a data transform field154B, whose content distinguishes which one of a number of datatransforms is to be performed (e.g., no data transform, swizzle,broadcast).

In the case of a memory access 120 instruction template of class A, thealpha field 152 is interpreted as an eviction hint field 152B, whosecontent distinguishes which one of the eviction hints is to be used (inFIG. 1A, temporal 152B.1 and non-temporal 152B.2 are respectivelyspecified for the memory access, temporal 125 instruction template andthe memory access, non-temporal 130 instruction template), while thebeta field 154 is interpreted as a data manipulation field 154C, whosecontent distinguishes which one of a number of data manipulationoperations (also known as primitives) is to be performed (e.g., nomanipulation; broadcast; up conversion of a source; and down conversionof a destination). The memory access 120 instruction templates includethe scale field 160, and optionally the displacement field 162A or thedisplacement scale field 162B.

Vector memory instructions perform vector loads from and vector storesto memory, with conversion support. As with regular vector instructions,vector memory instructions transfer data from/to memory in a dataelement-wise fashion, with the elements that are actually transferred isdictated by the contents of the vector mask that is selected as thewrite mask.

Memory Access Instruction Templates—Temporal

Temporal data is data likely to be reused soon enough to benefit fromcaching. This is, however, a hint, and different processors mayimplement it in different ways, including ignoring the hint entirely.

Memory Access Instruction Templates—Non-Temporal

Non-temporal data is data unlikely to be reused soon enough to benefitfrom caching in the 1st-level cache and should be given priority foreviction. This is, however, a hint, and different processors mayimplement it in different ways, including ignoring the hint entirely.

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field 152is interpreted as a write mask control (Z) field 152C, whose contentdistinguishes whether the write masking controlled by the write maskfield 170 should be a merging or a zeroing.

In the case of the non-memory access 105 instruction templates of classB, part of the beta field 154 is interpreted as an RL field 157A, whosecontent distinguishes which one of the different augmentation operationtypes are to be performed (e.g., round 157A.1 and vector length (VSIZE)157A.2 are respectively specified for the no memory access, write maskcontrol, partial round control type operation 112 instruction templateand the no memory access, write mask control, VSIZE type operation 117instruction template), while the rest of the beta field 154distinguishes which of the operations of the specified type is to beperformed. In the no memory access 105 instruction templates, the scalefield 160, the displacement field 162A, and the displacement scale filed162B are not present.

In the no memory access, write mask control, partial round control typeoperation 110 instruction template, the rest of the beta field 154 isinterpreted as a round operation field 159A and exception eventreporting is disabled (a given instruction does not report any kind offloating-point exception flag and does not raise any floating pointexception handler).

Round operation control field 159A—just as round operation control field158, its content distinguishes which one of a group of roundingoperations to perform (e.g., Round-up, Round-down, Round-towards-zeroand Round-to-nearest). Thus, the round operation control field 159Aallows for the changing of the rounding mode on a per instruction basis.In one embodiment of the invention where a processor includes a controlregister for specifying rounding modes, the round operation controlfield's 150 content overrides that register value.

In the no memory access, write mask control, VSIZE type operation 117instruction template, the rest of the beta field 154 is interpreted as avector length field 159B, whose content distinguishes which one of anumber of data vector lengths is to be performed on (e.g., 128, 256, or512 byte).

In the case of a memory access 120 instruction template of class B, partof the beta field 154 is interpreted as a broadcast field 157B, whosecontent distinguishes whether or not the broadcast type datamanipulation operation is to be performed, while the rest of the betafield 154 is interpreted the vector length field 159B. The memory access120 instruction templates include the scale field 160, and optionallythe displacement field 162A or the displacement scale field 162B.

With regard to the generic vector friendly instruction format 100, afull opcode field 174 is shown including the format field 140, the baseoperation field 142, and the data element width field 164. While oneembodiment is shown where the full opcode field 174 includes all ofthese fields, the full opcode field 174 includes less than all of thesefields in embodiments that do not support all of them. The full opcodefield 174 provides the operation code (opcode).

The augmentation operation field 150, the data element width field 164,and the write mask field 170 allow these features to be specified on aper instruction basis in the generic vector friendly instruction format.

The combination of write mask field and data element width field createtyped instructions in that they allow the mask to be applied based ondifferent data element widths.

The various instruction templates found within class A and class B arebeneficial in different situations. In some embodiments of theinvention, different processors or different cores within a processormay support only class A, only class B, or both classes. For instance, ahigh performance general purpose out-of-order core intended forgeneral-purpose computing may support only class B, a core intendedprimarily for graphics and/or scientific (throughput) computing maysupport only class A, and a core intended for both may support both (ofcourse, a core that has some mix of templates and instructions from bothclasses but not all templates and instructions from both classes iswithin the purview of the invention). Also, a single processor mayinclude multiple cores, all of which support the same class or in whichdifferent cores support different class. For instance, in a processorwith separate graphics and general purpose cores, one of the graphicscores intended primarily for graphics and/or scientific computing maysupport only class A, while one or more of the general purpose cores maybe high performance general purpose cores with out of order executionand register renaming intended for general-purpose computing thatsupport only class B. Another processor that does not have a separategraphics core, may include one more general purpose in-order orout-of-order cores that support both class A and class B. Of course,features from one class may also be implement in the other class indifferent embodiments of the invention. Programs written in a high levellanguage would be put (e.g., just in time compiled or staticallycompiled) into an variety of different executable forms, including: 1) aform having only instructions of the class(es) supported by the targetprocessor for execution; or 2) a form having alternative routineswritten using different combinations of the instructions of all classesand having control flow code that selects the routines to execute basedon the instructions supported by the processor which is currentlyexecuting the code.

B. Exemplary Specific Vector Friendly Instruction Format

FIG. 2 is a block diagram illustrating an exemplary specific vectorfriendly instruction format according to embodiments of the invention.FIG. 2 shows a specific vector friendly instruction format 200 that isspecific in the sense that it specifies the location, size,interpretation, and order of the fields, as well as values for some ofthose fields. The specific vector friendly instruction format 200 may beused to extend the x86 instruction set, and thus some of the fields aresimilar or the same as those used in the existing x86 instruction setand extension thereof (e.g., AVX). This format remains consistent withthe prefix encoding field, real opcode byte field, MOD R/M field, SIBfield, displacement field, and immediate fields of the existing x86instruction set with extensions. The fields from FIG. 1 into which thefields from FIG. 2 map are illustrated.

It should be understood that, although embodiments of the invention aredescribed with reference to the specific vector friendly instructionformat 200 in the context of the generic vector friendly instructionformat 100 for illustrative purposes, the invention is not limited tothe specific vector friendly instruction format 200 except whereclaimed. For example, the generic vector friendly instruction format 100contemplates a variety of possible sizes for the various fields, whilethe specific vector friendly instruction format 200 is shown as havingfields of specific sizes. By way of specific example, while the dataelement width field 164 is illustrated as a one bit field in thespecific vector friendly instruction format 200, the invention is not solimited (that is, the generic vector friendly instruction format 100contemplates other sizes of the data element width field 164).

The generic vector friendly instruction format 100 includes thefollowing fields listed below in the order illustrated in FIG. 2A.

EVEX Prefix (Bytes 0-3) 202—is encoded in a four-byte form.

Format Field 140 (EVEX Byte 0, bits [7:0])—the first byte (EVEX Byte 0)is the format field 140 and it contains 0x62 (the unique value used fordistinguishing the vector friendly instruction format in one embodimentof the invention).

The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fieldsproviding specific capability.

REX field 205 (EVEX Byte 1, bits [7-5])—consists of a EVEX.R bit field(EVEX Byte 1, bit [7]-R), EVEX.X bit field (EVEX byte 1, bit [6]-X), and157BEX byte 1, bit[5]-B). The EVEX.R, EVEX.X, and EVEX.B bit fieldsprovide the same functionality as the corresponding VEX bit fields, andare encoded using 1s complement form, i.e. ZMM0 is encoded as 1111B,ZMM15 is encoded as 0000B. Other fields of the instructions encode thelower three bits of the register indexes as is known in the art (rrr,xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by addingEVEX.R, EVEX.X, and EVEX.B.

REX′ field 110—this is the first part of the REX′ field 110 and is theEVEX.R′ bit field (EVEX Byte 1, bit [4]-R′) that is used to encodeeither the upper 16 or lower 16 of the extended 32 register set. In oneembodiment of the invention, this bit, along with others as indicatedbelow, is stored in bit inverted format to distinguish (in thewell-known x86 32-bit mode) from the BOUND instruction, whose realopcode byte is 62, but does not accept in the MOD R/M field (describedbelow) the value of 11 in the MOD field; alternative embodiments of theinvention do not store this and the other indicated bits below in theinverted format. A value of 1 is used to encode the lower 16 registers.In other words, R′Rrrr is formed by combining EVEX.R′, EVEX.R, and theother RRR from other fields.

Opcode map field 215 (EVEX byte 1, bits [3:0]-mmmm)—its content encodesan implied leading opcode byte (0F, 0F 38, or 0F 3).

Data element width field 164 (EVEX byte 2, bit [7]-W)—is represented bythe notation EVEX.W. EVEX.W is used to define the granularity (size) ofthe datatype (either 32-bit data elements or 64-bit data elements).

EVEX.vvvv 220 (EVEX Byte 2, bits [6:3]-vvvv)—the role of EVEX.vvvv mayinclude the following: 1) EVEX.vvvv encodes the first source registeroperand, specified in inverted (1s complement) form and is valid forinstructions with 2 or more source operands; 2) EVEX.vvvv encodes thedestination register operand, specified in 1s complement form forcertain vector shifts; or 3) EVEX.vvvv does not encode any operand, thefield is reserved and should contain 1111b. Thus, EVEX.vvvv field 220encodes the 4 low-order bits of the first source register specifierstored in inverted (1s complement) form. Depending on the instruction,an extra different EVEX bit field is used to extend the specifier sizeto 32 registers.

EVEX.U 168 Class field (EVEX byte 2, bit [2]-U)—If EVEX.U=0, itindicates class A or EVEX.U0; if EVEX.U=1, it indicates class B orEVEX.U1.

Prefix encoding field 225 (EVEX byte 2, bits [1:0]-pp)—providesadditional bits for the base operation field. In addition to providingsupport for the legacy SSE instructions in the EVEX prefix format, thisalso has the benefit of compacting the SIMD prefix (rather thanrequiring a byte to express the SIMD prefix, the EVEX prefix requiresonly 2 bits). In one embodiment, to support legacy SSE instructions thatuse a SIMD prefix (66H, F2H, F3H) in both the legacy format and in theEVEX prefix format, these legacy SIMD prefixes are encoded into the SIMDprefix encoding field; and at runtime are expanded into the legacy SIMDprefix prior to being provided to the decoder's PLA (so the PLA canexecute both the legacy and EVEX format of these legacy instructionswithout modification). Although newer instructions could use the EVEXprefix encoding field's content directly as an opcode extension, certainembodiments expand in a similar fashion for consistency but allow fordifferent meanings to be specified by these legacy SIMD prefixes. Analternative embodiment may redesign the PLA to support the 2 bit SIMDprefix encodings, and thus not require the expansion.

Alpha field 152 (EVEX byte 3, bit [7]-EH; also known as EVEX.EH,EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustratedwith α)—as previously described, this field is context specific.

Beta field 154 (EVEX byte 3, bits [6:4]-SSS, also known as EVEX.s₂₋₀,EVEX.r₂₋₀, EVEX.rr1, EVEX.LL0, EVEX.LLB; also illustrated with βββ)—aspreviously described, this field is context specific.

REX′ field 110—this is the remainder of the REX′ field and is theEVEX.V′ bit field (EVEX Byte 3, bit [3]-V′) that may be used to encodeeither the upper 16 or lower 16 of the extended 32 register set. Thisbit is stored in bit inverted format. A value of 1 is used to encode thelower 16 registers. In other words, V′VVVV is formed by combiningEVEX.V′, EVEX.vvvv.

Write mask field 170 (EVEX byte 3, bits [2:0]-kkk)—its content specifiesthe index of a register in the write mask registers as previouslydescribed. In one embodiment of the invention, the specific valueEVEX.kkk=000 has a special behavior implying no write mask is used forthe particular instruction (this may be implemented in a variety of waysincluding the use of a write mask hardwired to all ones or hardware thatbypasses the masking hardware).

Real Opcode Field 230 (Byte 4) is also known as the opcode byte. Part ofthe opcode is specified in this field.

MOD R/M Field 240 (Byte 5) includes MOD field 242, Reg field 244, andR/M field 246. As previously described, the MOD field's 242 contentdistinguishes between memory access and non-memory access operations.The role of Reg field 244 can be summarized to two situations: encodingeither the destination register operand or a source register operand, orbe treated as an opcode extension and not used to encode any instructionoperand. The role of R/M field 246 may include the following: encodingthe instruction operand that references a memory address, or encodingeither the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, thescale field's 150 content is used for memory address generation. SIB.xxx254 and SIB.bbb 256—the contents of these fields have been previouslyreferred to with regard to the register indexes Xxxx and Bbbb.

Displacement field 162A (Bytes 7-10)—when MOD field 242 contains 10,bytes 7-10 are the displacement field 162A, and it works the same as thelegacy 32-bit displacement (disp32) and works at byte granularity.

Displacement factor field 162B (Byte 7)—when MOD field 242 contains 01,byte 7 is the displacement factor field 162B. The location of this fieldis that same as that of the legacy x86 instruction set 8-bitdisplacement (disp8), which works at byte granularity. Since disp8 issign extended, it can only address between −128 and 127 bytes offsets;in terms of 64 byte cache lines, disp8 uses 8 bits that can be set toonly four really useful values −128, −64, 0, and 64; since a greaterrange is often needed, disp32 is used; however, disp32 requires 4 bytes.In contrast to disp8 and disp32, the displacement factor field 162B is areinterpretation of disp8; when using displacement factor field 162B,the actual displacement is determined by the content of the displacementfactor field multiplied by the size of the memory operand access (N).This type of displacement is referred to as disp8*N. This reduces theaverage instruction length (a single byte of used for the displacementbut with a much greater range). Such compressed displacement is based onthe assumption that the effective displacement is multiple of thegranularity of the memory access, and hence, the redundant low-orderbits of the address offset do not need to be encoded. In other words,the displacement factor field 162B substitutes the legacy x86instruction set 8-bit displacement. Thus, the displacement factor field162B is encoded the same way as an x86 instruction set 8-bitdisplacement (so no changes in the ModRM/SIB encoding rules) with theonly exception that disp8 is overloaded to disp8*N. In other words,there are no changes in the encoding rules or encoding lengths but onlyin the interpretation of the displacement value by hardware (which needsto scale the displacement by the size of the memory operand to obtain abyte-wise address offset).

Immediate field 172 operates as previously described.

Full Opcode Field

FIG. 2B is a block diagram illustrating the fields of the specificvector friendly instruction format 200 that make up the full opcodefield 174 according to one embodiment of the invention. Specifically,the full opcode field 174 includes the format field 140, the baseoperation field 142, and the data element width (W) field 164. The baseoperation field 142 includes the prefix encoding field 225, the opcodemap field 215, and the real opcode field 230.

Register Index Field

FIG. 2C is a block diagram illustrating the fields of the specificvector friendly instruction format 200 that make up the register indexfield 144 according to one embodiment of the invention. Specifically,the register index field 144 includes the REX field 205, the REX′ field210, the MODR/M.reg field 244, the MODR/M.r/m field 246, the VVVV field220, xxx field 254, and the bbb field 256.

Augmentation Operation Field

FIG. 2D is a block diagram illustrating the fields of the specificvector friendly instruction format 200 that make up the augmentationoperation field 150 according to one embodiment of the invention. Whenthe class (U) field 168 contains 0, it signifies EVEX.U0 (class A 168A);when it contains 1, it signifies EVEX.U1 (class B 168B). When U=0 andthe MOD field 242 contains 11 (signifying a no memory access operation),the alpha field 152 (EVEX byte 3, bit [7]-EH) is interpreted as the rsfield 152A. When the rs field 152A contains a 1 (round 152A.1), the betafield 154 (EVEX byte 3, bits [6:4]-SSS) is interpreted as the roundcontrol field 154A. The round control field 154A includes a one bit SAEfield 156 and a two bit round operation field 158. When the rs field152A contains a 0 (data transform 152A.2), the beta field 154 (EVEX byte3, bits [6:4]-SSS) is interpreted as a three bit data transform field154B. When U=0 and the MOD field 242 contains 00, 01, or 10 (signifyinga memory access operation), the alpha field 152 (EVEX byte 3, bit[7]-EH) is interpreted as the eviction hint (EH) field 152B and the betafield 154 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a three bitdata manipulation field 154C.

When U=1, the alpha field 152 (EVEX byte 3, bit [7]-EH) is interpretedas the write mask control (Z) field 152C. When U=1 and the MOD field 242contains 11 (signifying a no memory access operation), part of the betafield 154 (EVEX byte 3, bit [4]-S₀) is interpreted as the RL field 157A;when it contains a 1 (round 157A.1) the rest of the beta field 154 (EVEXbyte 3, bit [6-5]-S₂₋₁) is interpreted as the round operation field159A, while when the RL field 157A contains a 0 (VSIZE 157.A2) the restof the beta field 154 (EVEX byte 3, bit [6-5]-S₂₋₁) is interpreted asthe vector length field 159B (EVEX byte 3, bit [6-5]-L₁₋₀). When U=1 andthe MOD field 242 contains 00, 01, or 10 (signifying a memory accessoperation), the beta field 154 (EVEX byte 3, bits [6:4]-SSS) isinterpreted as the vector length field 159B (EVEX byte 3, bit[6-5]-L₁₋₀) and the broadcast field 157B (EVEX byte 3, bit [4]-B).

C. Exemplary Register Architecture

FIG. 3 is a block diagram of a register architecture 300 according toone embodiment of the invention. In the embodiment illustrated, thereare 32 vector registers 310 that are 512 bits wide; these registers arereferenced as zmm0 through zmm31. The lower order 256 bits of the lower16 zmm registers are overlaid on registers ymm0-16. The lower order 128bits of the lower 16 zmm registers (the lower order 128 bits of the ymmregisters) are overlaid on registers xmm0-15. The specific vectorfriendly instruction format 200 operates on these overlaid register fileas illustrated in the below tables.

Adjustable Vector Length Class Operations Registers Instruction A (FIG.110, 115, zmm registers (the Templates that do 1A; U = 0) 125, 130vector length is 64 not include the byte) vector length field B (FIG.112 zmm registers (the 159B 1B; U = 1) vector length is 64 byte)Instruction B (FIG. 117, 127 zmm, ymm, or xmm templates that do 1B; U= 1) registers (the vector include the vector length is 64 byte, 32length field 159B byte, or 16 byte) depending on the vector length field159B

In other words, the vector length field 159B selects between a maximumlength and one or more other shorter lengths, where each such shorterlength is half the length of the preceding length; and instructionstemplates without the vector length field 159B operate on the maximumvector length. Further, in one embodiment, the class B instructiontemplates of the specific vector friendly instruction format 200 operateon packed or scalar single/double-precision floating point data andpacked or scalar integer data. Scalar operations are operationsperformed on the lowest order data element position in an zmm/ymm/xmmregister; the higher order data element positions are either left thesame as they were prior to the instruction or zeroed depending on theembodiment.

Write mask registers 315—in the embodiment illustrated, there are 8write mask registers (k0 through k7), each 64 bits in size. In analternate embodiment, the write mask registers 315 are 16 bits in size.As previously described, in one embodiment of the invention, the vectormask register k0 cannot be used as a write mask; when the encoding thatwould normally indicate k0 is used for a write mask, it selects ahardwired write mask of 0xFFFF, effectively disabling write masking forthat instruction.

General-purpose registers 325—in the embodiment illustrated, there aresixteen 64-bit general-purpose registers that are used along with theexisting x86 addressing modes to address memory operands. Theseregisters are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI,RSP, and R8 through R15.

Scalar floating point stack register file (x87 stack) 345, on which isaliased the MMX packed integer flat register file 350—in the embodimentillustrated, the x87 stack is an eight-element stack used to performscalar floating-point operations on 32/64/80-bit floating point datausing the x87 instruction set extension; while the MMX registers areused to perform operations on 64-bit packed integer data, as well as tohold operands for some operations performed between the MMX and XMMregisters.

Alternative embodiments of the invention may use wider or narrowerregisters. Additionally, alternative embodiments of the invention mayuse more, less, or different register files and registers.

D. Exemplary Core Architectures, Processors, and Computer Architectures

Processor cores may be implemented in different ways, for differentpurposes, and in different processors. For instance, implementations ofsuch cores may include: 1) a general purpose in-order core intended forgeneral-purpose computing; 2) a high performance general purposeout-of-order core intended for general-purpose computing; 3) a specialpurpose core intended primarily for graphics and/or scientific(throughput) computing. Implementations of different processors mayinclude: 1) a CPU including one or more general purpose in-order coresintended for general-purpose computing and/or one or more generalpurpose out-of-order cores intended for general-purpose computing; and2) a coprocessor including one or more special purpose cores intendedprimarily for graphics and/or scientific (throughput). Such differentprocessors lead to different computer system architectures, which mayinclude: 1) the coprocessor on a separate chip from the CPU; 2) thecoprocessor on a separate die in the same package as a CPU; 3) thecoprocessor on the same die as a CPU (in which case, such a coprocessoris sometimes referred to as special purpose logic, such as integratedgraphics and/or scientific (throughput) logic, or as special purposecores); and 4) a system on a chip that may include on the same die thedescribed CPU (sometimes referred to as the application core(s) orapplication processor(s)), the above described coprocessor, andadditional functionality. Exemplary core architectures are describednext, followed by descriptions of exemplary processors and computerarchitectures.

FIG. 4A is a block diagram illustrating both an exemplary in-orderpipeline and an exemplary register renaming, out-of-orderissue/execution pipeline according to embodiments of the invention. FIG.4B is a block diagram illustrating both an exemplary embodiment of anin-order architecture core and an exemplary register renaming,out-of-order issue/execution architecture core to be included in aprocessor according to embodiments of the invention. The solid linedboxes in FIGS. 4A-B illustrate the in-order pipeline and in-order core,while the optional addition of the dashed lined boxes illustrates theregister renaming, out-of-order issue/execution pipeline and core. Giventhat the in-order aspect is a subset of the out-of-order aspect, theout-of-order aspect will be described.

In FIG. 4A, a processor pipeline 400 includes a fetch stage 402, alength decode stage 404, a decode stage 406, an allocation stage 408, arenaming stage 410, a scheduling (also known as a dispatch or issue)stage 412, a register read/memory read stage 414, an execute stage 416,a write back/memory write stage 418, an exception handling stage 422,and a commit stage 424.

FIG. 4B shows processor core 490 including a front end unit 430 coupledto an execution engine unit 450, and both are coupled to a memory unit470. The core 490 may be a reduced instruction set computing (RISC)core, a complex instruction set computing (CISC) core, a very longinstruction word (VLIW) core, or a hybrid or alternative core type. Asyet another option, the core 490 may be a special-purpose core, such as,for example, a network or communication core, compression engine,coprocessor core, general purpose computing graphics processing unit(GPGPU) core, graphics core, or the like.

The front end unit 430 includes a branch prediction unit 432 coupled toan instruction cache unit 434, which is coupled to an instructiontranslation lookaside buffer (TLB) 436, which is coupled to aninstruction fetch unit 438, which is coupled to a decode unit 440. Thedecode unit 440 (or decoder) may decode instructions, and generate as anoutput one or more micro-operations, micro-code entry points,microinstructions, other instructions, or other control signals, whichare decoded from, or which otherwise reflect, or are derived from, theoriginal instructions. The decode unit 440 may be implemented usingvarious different mechanisms. Examples of suitable mechanisms include,but are not limited to, look-up tables, hardware implementations,programmable logic arrays (PLAs), microcode read only memories (ROMs),etc. In one embodiment, the core 490 includes a microcode ROM or othermedium that stores microcode for certain macroinstructions (e.g., indecode unit 440 or otherwise within the front end unit 430). The decodeunit 440 is coupled to a rename/allocator unit 452 in the executionengine unit 450.

The execution engine unit 450 includes the rename/allocator unit 452coupled to a retirement unit 454 and a set of one or more schedulerunit(s) 456. The scheduler unit(s) 456 represents any number ofdifferent schedulers, including reservations stations, centralinstruction window, etc. The scheduler unit(s) 456 is coupled to thephysical register file(s) unit(s) 458. Each of the physical registerfile(s) units 458 represents one or more physical register files,different ones of which store one or more different data types, such asscalar integer, scalar floating point, packed integer, packed floatingpoint, vector integer, vector floating point, status (e.g., aninstruction pointer that is the address of the next instruction to beexecuted), etc. In one embodiment, the physical register file(s) unit458 comprises a vector registers unit, a write mask registers unit, anda scalar registers unit. These register units may provide architecturalvector registers, vector mask registers, and general purpose registers.The physical register file(s) unit(s) 458 is overlapped by theretirement unit 454 to illustrate various ways in which registerrenaming and out-of-order execution may be implemented (e.g., using areorder buffer(s) and a retirement register file(s); using a futurefile(s), a history buffer(s), and a retirement register file(s); using aregister maps and a pool of registers; etc.). The retirement unit 454and the physical register file(s) unit(s) 458 are coupled to theexecution cluster(s) 460. The execution cluster(s) 460 includes a set ofone or more execution units 462 and a set of one or more memory accessunits 464. The execution units 462 may perform various operations (e.g.,shifts, addition, subtraction, multiplication) and on various types ofdata (e.g., scalar floating point, packed integer, packed floatingpoint, vector integer, vector floating point). While some embodimentsmay include a number of execution units dedicated to specific functionsor sets of functions, other embodiments may include only one executionunit or multiple execution units that all perform all functions. Thescheduler unit(s) 456, physical register file(s) unit(s) 458, andexecution cluster(s) 460 are shown as being possibly plural becausecertain embodiments create separate pipelines for certain types ofdata/operations (e.g., a scalar integer pipeline, a scalar floatingpoint/packed integer/packed floating point/vector integer/vectorfloating point pipeline, and/or a memory access pipeline that each havetheir own scheduler unit, physical register file(s) unit, and/orexecution cluster—and in the case of a separate memory access pipeline,certain embodiments are implemented in which only the execution clusterof this pipeline has the memory access unit(s) 464). It should also beunderstood that where separate pipelines are used, one or more of thesepipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units 464 is coupled to the memory unit 470,which includes a data TLB unit 472 coupled to a data cache unit 474coupled to a level 2 (L2) cache unit 476. In one exemplary embodiment,the memory access units 464 may include a load unit, a store addressunit, and a store data unit, each of which is coupled to the data TLBunit 472 in the memory unit 470. The instruction cache unit 434 isfurther coupled to a level 2 (L2) cache unit 476 in the memory unit 470.The L2 cache unit 476 is coupled to one or more other levels of cacheand eventually to a main memory.

By way of example, the exemplary register renaming, out-of-orderissue/execution core architecture may implement the pipeline 400 asfollows: 1) the instruction fetch 438 performs the fetch and lengthdecoding stages 402 and 404; 2) the decode unit 440 performs the decodestage 406; 3) the rename/allocator unit 452 performs the allocationstage 408 and renaming stage 410; 4) the scheduler unit(s) 456 performsthe schedule stage 412; 5) the physical register file(s) unit(s) 458 andthe memory unit 470 perform the register read/memory read stage 414; theexecution cluster 460 perform the execute stage 416; 6) the memory unit470 and the physical register file(s) unit(s) 458 perform the writeback/memory write stage 418; 7) various units may be involved in theexception handling stage 422; and 8) the retirement unit 454 and thephysical register file(s) unit(s) 458 perform the commit stage 424.

The core 490 may support one or more instructions sets (e.g., the x86instruction set (with some extensions that have been added with newerversions); the MIPS instruction set of MIPS Technologies of Sunnyvale,Calif.; the ARM instruction set (with optional additional extensionssuch as NEON) of ARM Holdings of Sunnyvale, Calif.), including theinstruction(s) described herein. In one embodiment, the core 490includes logic to support a packed data instruction set extension (e.g.,AVX1, AVX2), thereby allowing the operations used by many multimediaapplications to be performed using packed data.

It should be understood that the core may support multithreading(executing two or more parallel sets of operations or threads), and maydo so in a variety of ways including time sliced multithreading,simultaneous multithreading (where a single physical core provides alogical core for each of the threads that physical core issimultaneously multithreading), or a combination thereof (e.g., timesliced fetching and decoding and simultaneous multithreading thereaftersuch as in the Intel® Hyperthreading technology).

While register renaming is described in the context of out-of-orderexecution, it should be understood that register renaming may be used inan in-order architecture. While the illustrated embodiment of theprocessor also includes separate instruction and data cache units434/474 and a shared L2 cache unit 476, alternative embodiments may havea single internal cache for both instructions and data, such as, forexample, a Level 1 (L1) internal cache, or multiple levels of internalcache. In some embodiments, the system may include a combination of aninternal cache and an external cache that is external to the core and/orthe processor. Alternatively, all of the cache may be external to thecore and/or the processor.

FIGS. 5A-B illustrate a block diagram of a more specific exemplaryin-order core architecture, which core would be one of several logicblocks (including other cores of the same type and/or different types)in a chip. The logic blocks communicate through a high-bandwidthinterconnect network (e.g., a ring network) with some fixed functionlogic, memory I/O interfaces, and other necessary I/O logic, dependingon the application.

FIG. 5A is a block diagram of a single processor core, along with itsconnection to the on-die interconnect network 502 and with its localsubset of the Level 2 (L2) cache 504, according to embodiments of theinvention. In one embodiment, an instruction decoder 500 supports thex86 instruction set with a packed data instruction set extension. An L1cache 506 allows low-latency accesses to cache memory into the scalarand vector units. While in one embodiment (to simplify the design), ascalar unit 508 and a vector unit 510 use separate register sets(respectively, scalar registers 512 and vector registers 514) and datatransferred between them is written to memory and then read back in froma level 1 (L1) cache 506, alternative embodiments of the invention mayuse a different approach (e.g., use a single register set or include acommunication path that allow data to be transferred between the tworegister files without being written and read back).

The local subset of the L2 cache 504 is part of a global L2 cache thatis divided into separate local subsets, one per processor core. Eachprocessor core has a direct access path to its own local subset of theL2 cache 504. Data read by a processor core is stored in its L2 cachesubset 504 and can be accessed quickly, in parallel with other processorcores accessing their own local L2 cache subsets. Data written by aprocessor core is stored in its own L2 cache subset 504 and is flushedfrom other subsets, if necessary. The ring network ensures coherency forshared data. The ring network is bi-directional to allow agents such asprocessor cores, L2 caches and other logic blocks to communicate witheach other within the chip. Each ring data-path is 1012-bits wide perdirection.

FIG. 5B is an expanded view of part of the processor core in FIG. 5Aaccording to embodiments of the invention. FIG. 5B includes an L1 datacache 506A part of the L1 cache 504, as well as more detail regardingthe vector unit 510 and the vector registers 514. Specifically, thevector unit 510 is a 16-wide vector processing unit (VPU) (see the16-wide ALU 528), which executes one or more of integer,single-precision float, and double-precision float instructions. The VPUsupports swizzling the register inputs with swizzle unit 520, numericconversion with numeric convert units 522A-B, and replication withreplication unit 524 on the memory input. Write mask registers 526 allowpredicating resulting vector writes.

FIG. 6 is a block diagram of a processor 600 that may have more than onecore, may have an integrated memory controller, and may have integratedgraphics according to embodiments of the invention. The solid linedboxes in FIG. 6 illustrate a processor 600 with a single core 602A, asystem agent 610, a set of one or more bus controller units 616, whilethe optional addition of the dashed lined boxes illustrates analternative processor 600 with multiple cores 602A-N, a set of one ormore integrated memory controller unit(s) 614 in the system agent unit610, and special purpose logic 608.

Thus, different implementations of the processor 600 may include: 1) aCPU with the special purpose logic 608 being integrated graphics and/orscientific (throughput) logic (which may include one or more cores), andthe cores 602A-N being one or more general purpose cores (e.g., generalpurpose in-order cores, general purpose out-of-order cores, acombination of the two); 2) a coprocessor with the cores 602A-N being alarge number of special purpose cores intended primarily for graphicsand/or scientific (throughput); and 3) a coprocessor with the cores602A-N being a large number of general purpose in-order cores. Thus, theprocessor 600 may be a general-purpose processor, coprocessor orspecial-purpose processor, such as, for example, a network orcommunication processor, compression engine, graphics processor, GPGPU(general purpose graphics processing unit), a high-throughput manyintegrated core (MIC) coprocessor (including 30 or more cores), embeddedprocessor, or the like. The processor may be implemented on one or morechips. The processor 600 may be a part of and/or may be implemented onone or more substrates using any of a number of process technologies,such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within thecores, a set or one or more shared cache units 606, and external memory(not shown) coupled to the set of integrated memory controller units614. The set of shared cache units 606 may include one or more mid-levelcaches, such as level 2 (L2), level 3 (L3), level 4 (L4), or otherlevels of cache, a last level cache (LLC), and/or combinations thereof.While in one embodiment a ring based interconnect unit 612 interconnectsthe integrated graphics logic 608, the set of shared cache units 606,and the system agent unit 610/integrated memory controller unit(s) 614,alternative embodiments may use any number of well-known techniques forinterconnecting such units. In one embodiment, coherency is maintainedbetween one or more cache units 606 and cores 602-A-N.

In some embodiments, one or more of the cores 602A-N are capable ofmulti-threading. The system agent 610 includes those componentscoordinating and operating cores 602A-N. The system agent unit 610 mayinclude for example a power control unit (PCU) and a display unit. ThePCU may be or include logic and components needed for regulating thepower state of the cores 602A-N and the integrated graphics logic 608.The display unit is for driving one or more externally connecteddisplays.

The cores 602A-N may be homogenous or heterogeneous in terms ofarchitecture instruction set; that is, two or more of the cores 602A-Nmay be capable of execution the same instruction set, while others maybe capable of executing only a subset of that instruction set or adifferent instruction set.

FIGS. 7-10 are block diagrams of exemplary computer architectures. Othersystem designs and configurations known in the arts for laptops,desktops, handheld PCs, personal digital assistants, engineeringworkstations, servers, network devices, network hubs, switches, embeddedprocessors, digital signal processors (DSPs), graphics devices, videogame devices, set-top boxes, micro controllers, cell phones, portablemedia players, hand held devices, and various other electronic devices,are also suitable. In general, a huge variety of systems or electronicdevices capable of incorporating a processor and/or other executionlogic as disclosed herein are generally suitable.

Referring now to FIG. 7, shown is a block diagram of a system 700 inaccordance with one embodiment of the present invention. The system 700may include one or more processors 710, 715, which are coupled to acontroller hub 720. In one embodiment the controller hub 720 includes agraphics memory controller hub (GMCH) 790 and an Input/Output Hub (IOH)750 (which may be on separate chips); the GMCH 790 includes memory andgraphics controllers to which are coupled memory 740 and a coprocessor745; the IOH 750 is couples input/output (I/O) devices 760 to the GMCH790. Alternatively, one or both of the memory and graphics controllersare integrated within the processor (as described herein), the memory740 and the coprocessor 745 are coupled directly to the processor 710,and the controller hub 720 in a single chip with the IOH 750.

The optional nature of additional processors 715 is denoted in FIG. 7with broken lines. Each processor 710, 715 may include one or more ofthe processing cores described herein and may be some version of theprocessor 600.

The memory 740 may be, for example, dynamic random access memory (DRAM),phase change memory (PCM), or a combination of the two. For at least oneembodiment, the controller hub 720 communicates with the processor(s)710, 715 via a multi-drop bus, such as a frontside bus (FSB),point-to-point interface such as QuickPath Interconnect (QPI), orsimilar connection 795.

In one embodiment, the coprocessor 745 is a special-purpose processor,such as, for example, a high-throughput MIC processor, a network orcommunication processor, compression engine, graphics processor, GPGPU,embedded processor, or the like. In one embodiment, controller hub 720may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources710, 715 in terms of a spectrum of metrics of merit includingarchitectural, microarchitectural, thermal, power consumptioncharacteristics, and the like.

In one embodiment, the processor 710 executes instructions that controldata processing operations of a general type. Embedded within theinstructions may be coprocessor instructions. The processor 710recognizes these coprocessor instructions as being of a type that shouldbe executed by the attached coprocessor 745. Accordingly, the processor710 issues these coprocessor instructions (or control signalsrepresenting coprocessor instructions) on a coprocessor bus or otherinterconnect, to coprocessor 745. Coprocessor(s) 745 accept and executethe received coprocessor instructions.

Referring now to FIG. 8, shown is a block diagram of a first morespecific exemplary system 800 in accordance with an embodiment of thepresent invention. As shown in FIG. 8, multiprocessor system 800 is apoint-to-point interconnect system, and includes a first processor 870and a second processor 880 coupled via a point-to-point interconnect850. Each of processors 870 and 880 may be some version of the processor600. In one embodiment of the invention, processors 870 and 880 arerespectively processors 710 and 715, while coprocessor 838 iscoprocessor 745. In another embodiment, processors 870 and 880 arerespectively processor 710 coprocessor 745.

Processors 870 and 880 are shown including integrated memory controller(IMC) units 872 and 882, respectively. Processor 870 also includes aspart of its bus controller units point-to-point (P-P) interfaces 876 and878; similarly, second processor 880 includes P-P interfaces 886 and888. Processors 870, 880 may exchange information via a point-to-point(P-P) interface 850 using P-P interface circuits 878, 888. As shown inFIG. 8, IMCs 872 and 882 couple the processors to respective memories,namely a memory 832 and a memory 834, which may be portions of mainmemory locally attached to the respective processors.

Processors 870, 880 may each exchange information with a chipset 890 viaindividual P-P interfaces 852, 854 using point to point interfacecircuits 876, 894, 886, 898. Chipset 890 may optionally exchangeinformation with the coprocessor 838 via a high-performance interface839. In one embodiment, the coprocessor 838 is a special-purposeprocessor, such as, for example, a high-throughput MIC processor, anetwork or communication processor, compression engine, graphicsprocessor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor oroutside of both processors, yet connected with the processors via P-Pinterconnect, such that either or both processors' local cacheinformation may be stored in the shared cache if a processor is placedinto a low power mode.

Chipset 890 may be coupled to a first bus 816 via an interface 896. Inone embodiment, first bus 816 may be a Peripheral Component Interconnect(PCI) bus, or a bus such as a PCI Express bus or another thirdgeneration I/O interconnect bus, although the scope of the presentinvention is not so limited.

As shown in FIG. 8, various I/O devices 814 may be coupled to first bus816, along with a bus bridge 818 which couples first bus 816 to a secondbus 820. In one embodiment, one or more additional processor(s) 815,such as coprocessors, high-throughput MIC processors, GPGPU's,accelerators (such as, e.g., graphics accelerators or digital signalprocessing (DSP) units), field programmable gate arrays, or any otherprocessor, are coupled to first bus 816. In one embodiment, second bus820 may be a low pin count (LPC) bus. Various devices may be coupled toa second bus 820 including, for example, a keyboard and/or mouse 822,communication devices 827 and a storage unit 828 such as a disk drive orother mass storage device which may include instructions/code and data830, in one embodiment. Further, an audio I/O 824 may be coupled to thesecond bus 820. Note that other architectures are possible. For example,instead of the point-to-point architecture of FIG. 8, a system mayimplement a multi-drop bus or other such architecture.

Referring now to FIG. 9, shown is a block diagram of a second morespecific exemplary system 900 in accordance with an embodiment of thepresent invention. Like elements in FIGS. 8 and 9 bear like referencenumerals, and certain aspects of FIG. 8 have been omitted from FIG. 9 inorder to avoid obscuring other aspects of FIG. 9.

FIG. 9 illustrates that the processors 870, 880 may include integratedmemory and I/O control logic (“CL”) 872 and 882, respectively. Thus, theCL 872, 882 include integrated memory controller units and include I/Ocontrol logic. FIG. 9 illustrates that not only are the memories 832,834 coupled to the CL 872, 882, but also that I/O devices 914 are alsocoupled to the control logic 872, 882. Legacy I/O devices 915 arecoupled to the chipset 890.

Referring now to FIG. 10, shown is a block diagram of a SoC 1000 inaccordance with an embodiment of the present invention. Similar elementsin FIG. 6 bear like reference numerals. Also, dashed lined boxes areoptional features on more advanced SoCs. In FIG. 10, an interconnectunit(s) 1002 is coupled to: an application processor 1010 which includesa set of one or more cores 202A-N and shared cache unit(s) 606; a systemagent unit 610; a bus controller unit(s) 616; an integrated memorycontroller unit(s) 614; a set or one or more coprocessors 1020 which mayinclude integrated graphics logic, an image processor, an audioprocessor, and a video processor; an static random access memory (SRAM)unit 1030; a direct memory access (DMA) unit 1032; and a display unit1040 for coupling to one or more external displays. In one embodiment,the coprocessor(s) 1020 include a special-purpose processor, such as,for example, a network or communication processor, compression engine,GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented inhardware, software, firmware, or a combination of such implementationapproaches. Embodiments of the invention may be implemented as computerprograms or program code executing on programmable systems comprising atleast one processor, a storage system (including volatile andnon-volatile memory and/or storage elements), at least one input device,and at least one output device.

Program code, such as code 830 illustrated in FIG. 8, may be applied toinput instructions to perform the functions described herein andgenerate output information. The output information may be applied toone or more output devices, in known fashion. For purposes of thisapplication, a processing system includes any system that has aprocessor, such as, for example; a digital signal processor (DSP), amicrocontroller, an application specific integrated circuit (ASIC), or amicroprocessor.

The program code may be implemented in a high level procedural or objectoriented programming language to communicate with a processing system.The program code may also be implemented in assembly or machinelanguage, if desired. In fact, the mechanisms described herein are notlimited in scope to any particular programming language. In any case,the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented byrepresentative instructions stored on a machine-readable medium whichrepresents various logic within the processor, which when read by amachine causes the machine to fabricate logic to perform the techniquesdescribed herein. Such representations, known as “IP cores” may bestored on a tangible, machine readable medium and supplied to variouscustomers or manufacturing facilities to load into the fabricationmachines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation,non-transitory, tangible arrangements of articles manufactured or formedby a machine or device, including storage media such as hard disks, anyother type of disk including floppy disks, optical disks, compact diskread-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), andmagneto-optical disks, semiconductor devices such as read-only memories(ROMs), random access memories (RAMs) such as dynamic random accessmemories (DRAMs), static random access memories (SRAMs), erasableprogrammable read-only memories (EPROMs), flash memories, electricallyerasable programmable read-only memories (EEPROMs), phase change memory(PCM), magnetic or optical cards, or any other type of media suitablefor storing electronic instructions.

Accordingly, embodiments of the invention also include non-transitory,tangible machine-readable media containing instructions or containingdesign data, such as Hardware Description Language (HDL), which definesstructures, circuits, apparatuses, processors and/or system featuresdescribed herein. Such embodiments may also be referred to as programproducts.

In some cases, an instruction converter may be used to convert aninstruction from a source instruction set to a target instruction set.For example, the instruction converter may translate (e.g., using staticbinary translation, dynamic binary translation including dynamiccompilation), morph, emulate, or otherwise convert an instruction to oneor more other instructions to be processed by the core. The instructionconverter may be implemented in software, hardware, firmware, or acombination thereof. The instruction converter may be on processor, offprocessor, or part on and part off processor.

FIG. 11 is a block diagram contrasting the use of a software instructionconverter to convert binary instructions in a source instruction set tobinary instructions in a target instruction set according to embodimentsof the invention. In the illustrated embodiment, the instructionconverter is a software instruction converter, although alternativelythe instruction converter may be implemented in software, firmware,hardware, or various combinations thereof. FIG. 11 shows a program in ahigh level language 1102 may be compiled using an x86 compiler 1104 togenerate x86 binary code 1106 that may be natively executed by aprocessor with at least one x86 instruction set core 1116. The processorwith at least one x86 instruction set core 1116 represents any processorthat can perform substantially the same functions as an Intel processorwith at least one x86 instruction set core by compatibly executing orotherwise processing (1) a substantial portion of the instruction set ofthe Intel x86 instruction set core or (2) object code versions ofapplications or other software targeted to run on an Intel processorwith at least one x86 instruction set core, in order to achievesubstantially the same result as an Intel processor with at least onex86 instruction set core. The x86 compiler 1104 represents a compilerthat is operable to generate x86 binary code 1106 (e.g., object code)that can, with or without additional linkage processing, be executed onthe processor with at least one x86 instruction set core 1116.Similarly, FIG. 11 shows the program in the high level language 1102 maybe compiled using an alternative instruction set compiler 1108 togenerate alternative instruction set binary code 1110 that may benatively executed by a processor without at least one x86 instructionset core 1114 (e.g., a processor with cores that execute the MIPSinstruction set of MIPS Technologies of Sunnyvale, Calif. and/or thatexecute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.).The instruction converter 1112 is used to convert the x86 binary code1106 into code that may be natively executed by the processor without anx86 instruction set core 1114. This converted code is not likely to bethe same as the alternative instruction set binary code 1110 because aninstruction converter capable of this is difficult to make; however, theconverted code will accomplish the general operation and be made up ofinstructions from the alternative instruction set. Thus, the instructionconverter 1112 represents software, firmware, hardware, or a combinationthereof that, through emulation, simulation or any other process, allowsa processor or other electronic device that does not have an x86instruction set processor or core to execute the x86 binary code 1106.

Apparatus and Method for Processing Sparse Data

Overview

In some implementations, an accelerator is coupled to processor cores orother processing elements to accelerate certain types of operations suchas graphics operations, machine-learning operations, pattern analysisoperations, and (as described in detail below) sparse matrixmultiplication operations, to name a few. The accelerator may becommunicatively coupled to the processor/cores over a bus or otherinterconnect (e.g., a point-to-point interconnect) or may be integratedon the same chip as the processor and communicatively coupled to thecores over an internal processor bus/interconnect. Regardless of themanner in which the accelerator is connected, the processor cores mayallocate certain processing tasks to the accelerator (e.g., in the formof sequences of instructions or uops) which includes dedicatedcircuitry/logic for efficiently processing these tasks.

Accelerator Architecture for Sparse Matrix and Vector Operations

FIG. 12 illustrates an exemplary implementation in which an accelerator1200 is communicatively coupled to a plurality of cores 1210-1211through a cache coherent interface 1230. Each of the cores 1210-1211includes a translation lookaside buffer 1212-1213 for storing virtual tophysical address translations and one or more caches 1214-1215 (e.g., L1cache, L2 cache, etc) for caching data and instructions. A memorymanagement unit 1220 manages access by the cores 1210-1211 to systemmemory 1250 which may be a dynamic random access memory DRAM. A sharedcache 1226 such as an L3 cache may be shared among the processor cores1210-1211 and with the accelerator 1200 via the cache coherent interface1230. In one implementation, the cores ATA1010T-1011, MMU 1220 and cachecoherent interface 1230 are integrated on a single processor chip.

The illustrated accelerator 1200 includes a data management unit 1205with a cache 1207 and scheduler 1206 for scheduling operations to aplurality of processing elements 1201-1202, N. In the illustratedimplementation, each processing element has its own local memory1203-1204, N. As described in detail below, each local memory 1203-1204,N may be implemented as a stacked DRAM or high bandwidth memory (HBM).

In one implementation, the cache coherent interface 1230 providescache-coherent connectivity between the cores 1210-1211 and theaccelerator 1200, in effect treating the accelerator as a peer of thecores 1210-1211. For example, the cache coherent interface 1230 mayimplement a cache coherency protocol to ensure that dataaccessed/modified by the accelerator 1200 and stored in the acceleratorcache 1207 and/or local memories 1203-1204, N is coherent with the datastored in the core caches 1210-1211, the shared cache 1226 and thesystem memory 1250. For example, the cache coherent interface 1230 mayparticipate in the snooping mechanisms used by the cores 1210-1211 andMMU 1220 to detect the state of cache lines within the shared cache 1226and local caches 1214-1215 and may act as a proxy, providing snoopupdates in response to accesses and attempted modifications to cachelines by the processing elements 1201-1202, N. In addition, when a cacheline is modified by the processing elements 1201-1202, N, the cachecoherent interface 1230 may update the status of the cache lines if theyare stored within the shared cache 1226 or local caches 1214-1215.

In addition, to reduce the data traffic between the cores 1210-1211 andaccelerator 1200, one embodiment tags data with an accelerator bias or aprocessor bias such as by setting a bit within a bias table at thegranularity of a memory page. Memory pages with an accelerator bias maybe processed by the accelerator 1200 without fully implementing thecache coherency protocol. The cores 1210-1211 will then refrain frommodifying pages that have an accelerator bias without first notifyingthe accelerator 1200.

In one implementation, the data management unit 1005 includes memorymanagement circuitry providing the accelerator 1200 access to systemmemory 1250 and the shared cache 1226. In addition, the data managementunit 1205 may provide updates to the cache coherent interface 1230 andreceiving updates from the cache coherent interface 1230 as needed(e.g., to determine state changes to cache lines). In the illustratedimplementation, the data management unit 1205 includes a scheduler 1205for scheduling instructions/operations to be executed by the processingelements 1201-1202, N. To perform its scheduling operations, thescheduler 1206 may evaluate dependences between instructions/operationsto ensure that instructions/operations are executed in a coherent order(e.g., to ensure that a first instruction executes before a secondinstruction which is dependent on results from the first instruction).Instructions/operations which are not inter-dependent may be executed inparallel on the processing elements 1201-1202, N.

FIG. 13 illustrates another view of accelerator 1200 and othercomponents previously described including a data management unit 1205, aplurality of processing elements 1201-N, and fast on-chip storage 1300(e.g., implemented using stacked local DRAM in one implementation). Inone implementation, the accelerator 1200 is a hardware acceleratorarchitecture and the processing elements 1201-N include circuitry forperforming matrix*vector and vector*vector operations, includingoperations for sparse/dense matrices. In particular, the processingelements 1201-N may include hardware support for column and row-orientedmatrix processing and may include microarchitectural support for a“scale and update” operation such as that used in machine learning (ML)algorithms.

The described implementations perform matrix/vector operations which areoptimized by keeping frequently used, randomly accessed, potentiallysparse (e.g., gather/scatter) vector data in the fast on-chip storage1300 and maintaining large, infrequently used matrix data in off-chipmemory (e.g., system memory 1250), accessed in a streaming fashionwhenever possible, and exposing intra/inter matrix block parallelism toscale up.

Implementations of the processing elements 1201-N process differentcombinations of sparse matrixes, dense matrices, sparse vectors, anddense vectors. As used herein, a “sparse” matrix or vector is a matrixor vector in which most of the elements are zero. By contrast, a “dense”matrix or vector is a matrix or vector in which most of the elements arenon-zero. The “sparsity” of a matrix/vector may be defined based on thenumber of zero-valued elements divided by the total number of elements(e.g., m×n for an m×n matrix). In one implementation, a matrix/vector isconsidered “sparse” if its sparsity if above a specified threshold.

An exemplary set of operations performed by the processing elements1201-N is illustrated in the table in FIG. 14. In particular theoperation types include a first multiply 1400 using a sparse matrix, asecond multiply 1401 using a dense matrix, a scale and update operation1402 m and a dot product operation 1403. Columns are provided for afirst input operand 1410 and a second input operand 1411 (each of whichmay include sparse or dense matrix/vector); an output format 1413 (e.g.,dense vector or scalar); a matrix data format (e.g., compressed sparserow, compressed sparse column, row-oriented, etc); and an operationidentifier 1414.

The runtime-dominating compute patterns found in some current workloadsinclude variations of matrix multiplication against a vector inrow-oriented and column-oriented fashion. They work on well-known matrixformats: compressed sparse row (CSR) and compressed sparse column (CSC).FIG. 15a depicts an example of a multiplication between a sparse matrixA against a vector x to produce a vector y. FIG. 15b illustrates the CSRrepresentation of matrix A in which each value is stored as a (value,row index) pair. For example, the (3,2) for row0 indicates that a valueof 3 is stored in element position 2 for row 0. FIG. 15c illustrates aCSC representation of matrix A which uses a (value, column index) pair.

FIGS. 16a, 16b, and 16c illustrate pseudo code of each compute pattern,which is described below in detail. In particular, FIG. 16a illustratesa row-oriented sparse matrix dense vector multiply (spMdV_csr); FIG. 16billustrates a column-oriented sparse matrix sparse vector multiply(spMspC_csc); and FIG. 16c illustrates a scale and update operation(scale_update).

A. Row-Oriented Sparse Matrix Dense Vector Multiplication (spMdV_csr)

This is a well-known compute pattern that is important in manyapplication domains such as high-performance computing. Here, for eachrow of matrix A, a dot product of that row against vector x isperformed, and the result is stored in the y vector element pointed toby the row index. This computation is used in a machine-learning (ML)algorithm that performs analysis across a set of samples (i.e., rows ofthe matrix). It may be used in techniques such as “mini-batch.” Thereare also cases where ML algorithms perform only a dot product of asparse vector against a dense vector (i.e., an iteration of thespMdV_csr loop), such as in the stochastic variants of learningalgorithms.

A known factor that can affect performance on this computation is theneed to randomly access sparse x vector elements in the dot productcomputation. For a conventional server system, when the x vector islarge, this would result in irregular accesses (gather) to memory orlast level cache.

To address this, one implementation of a processing element dividesmatrix A into column blocks and the x vector into multiple subsets (eachcorresponding to an A matrix column block). The block size can be chosenso that the x vector subset can fit on chip. Hence, random accesses toit can be localized on-chip.

B. Column-Oriented Sparse Matrix Sparse Vector Multiplication(spMspV_csc)

This pattern that multiplies a sparse matrix against a sparse vector isnot as well-known as spMdV_csr. However, it is important in some MLalgorithms. It is used when an algorithm works on a set of features,which are represented as matrix columns in the dataset (hence, the needfor column-oriented matrix accesses).

In this compute pattern, each column of the matrix A is read andmultiplied against the corresponding non-zero element of vector x. Theresult is used to update partial dot products that are kept at the yvector. After all the columns associated with non-zero x vector elementshave been processed, the y vector will contain the final dot products.

While accesses to matrix A is regular (i.e., stream in columns of A),the accesses to the y vector to update the partial dot products isirregular. The y element to access depends on the row index of the Avector element being processed. To address this, the matrix A can bedivided into row blocks. Consequently, the vector y can be divided intosubsets corresponding to these blocks. This way, when processing amatrix row block, it only needs to irregularly access (gather/scatter)its y vector subset. By choosing the block size properly, the y vectorsubset can be kept on-chip.

C. Scale and Update (Scale_Update)

This pattern is typically used by ML algorithms to apply scaling factorsto each sample in the matrix and reduced them into a set of weights,each corresponding to a feature (i.e., a column in A). Here, the xvector contains the scaling factors. For each row of matrix A (in CSRformat), the scaling factors for that row are read from the x vector,and then applied to each element of A in that row. The result is used toupdate the element of y vector. After all rows have been processed, they vector contains the reduced weights.

Similar to prior compute patterns, the irregular accesses to the yvector could affect performance when y is large. Dividing matrix A intocolumn blocks and y vector into multiple subsets corresponding to theseblocks can help localize the irregular accesses within each y subset.

Processor Element Architecture for Sparse Matrix and Vector Operations

FIG. 17 illustrates one implementation of a hardware accelerator 1200that can efficiently perform the compute patterns discussed above. Theaccelerator 1200 may be a hardware IP block that can be integrated withgeneral purpose processors, similar to those found in existingaccelerator-based solutions. In one implementation, the accelerator 1200independently accesses memory 1250 through an interconnect shared withthe processors to perform the compute patterns. It supports anyarbitrarily large matrix datasets that reside in off-chip memory.

FIG. 17 illustrates an architecture and processing flow for oneimplementation of the data management unit 1205 and the processingelements 1201-1202. In this implementation, the data management unit1205 includes a processing element scheduler 1701, a read buffer 1702, awrite buffer 1703 and a reduction unit 1704. Each PE 1201-1202 includesan input buffer 1705-1706, a multiplier 1707-1708, an adder 1709-1710, alocal RAM 1721-1722, a sum register 1711-1712, and an output buffer1713-1714.

The accelerator supports the matrix blocking schemes discussed above(i.e., row and column blocking) to support any arbitrarily large matrixdata. The accelerator is designed to process a block of matrix data.Each block is further divided into sub-blocks which are processed inparallel by the PEs 1201-1202.

In operation, the data management unit 1205 reads the matrix rows orcolumns from the memory subsystem into its read buffer 1702, which isthen dynamically distributed by the PE scheduler 1701 across PEs1201-1202 for processing. It also writes results to memory from itswrite buffer 1703.

Each PE 1201-1202 is responsible for processing a matrix sub-block. A PEcontains an on-chip RAM 1721-1722 to store the vector that needs to beaccessed randomly (i.e., a subset of x or y vector, as described above).It also contains a floating point multiply-accumulate (FMA) unitincluding multiplier 1707-1708 and adder 1709-1710 and unpack logicwithin input buffers 1705-1706 to extract matrix elements from inputdata, and a sum register 1711-1712 to keep the accumulated FMA results.

One implementation of the accelerator 1200 achieves extreme efficienciesbecause (1) it places sparse, irregularly accessed (gather/scatter) datain on-chip PE RAMs 1721-1722, (2) it utilizes a hardware PE scheduler1701 to ensure PEs are well utilized, and (3) unlike with generalpurpose processors, the accelerator includes only the hardware resourcesthat are essential for sparse matrix operations. Overall, theaccelerator efficiently converts the available memory bandwidth providedto it into performance.

Scaling of performance can be done by employing more PEs in anaccelerator block to process multiple matrix sub-blocks in parallel,and/or employing more accelerator blocks (each has a set of PEs) toprocess multiple matrix blocks in parallel. A combination of theseoptions is considered below. The number of PEs and/or accelerator blocksshould be tuned to match the memory bandwidth.

One implementation of the accelerator 1200 can be programmed through asoftware library (similar to Intel® Math Kernel Library). Such libraryprepares the matrix data in memory, sets control registers in theaccelerator 1200 with information about the computation (e.g.,computation type, memory pointer to matrix data), and starts theaccelerator. Then, the accelerator independently accesses matrix data inmemory, performs the computation, and writes the results back to memoryfor the software to consume.

The accelerator handles the different compute patterns by setting itsPEs to the proper datapath configuration, as depicted in FIGS. 18A-B. Inparticular, FIG. 18a highlights paths (using dotted lines) forspMspV_csc and scale_update operations and FIG. 18b illustrates pathsfor a spMdV_csr operation. The accelerator operation to perform eachcompute pattern is detailed below.

For spMspV_csc, the initial y vector subset is loaded in to PE's RAM1721 by the DMU 1205. It then reads x vector elements from memory. Foreach x element, the DMU 1205 streams the elements of the correspondingmatrix column from memory and supplies them to the PE 1201. Each matrixelement contains a value (A.val) and an index (A.idx) which points tothe y element to read from PE's RAM 1721. The DMU 1005 also provides thex vector element (x.val) that is multiplied against A.val by themultiply-accumulate (FMA) unit. The result is used to update the yelement in the PE's RAM pointed to by A.idx. Note that even though notused by our workloads, the accelerator also supports column-wisemultiplication against a dense x vector (spMdV_csc) by processing allmatrix columns instead of only a subset (since x is dense).

The scale_update operation is similar to the spMspV_csc, except that theDMU 1205 reads the rows of an A matrix represented in a CSR formatinstead of a CSC format. For the spMdV_csr, the x vector subset isloaded in to the PE's RAM 1721. DMU 1205 streams in matrix row elements(i.e., {A.val,A.idx} pairs) from memory. A.idx is used to read theappropriate x vector element from RAM 1721, which is multiplied againstA.val by the FMA. Results are accumulated into the sum register 1712.The sum register is written to the output buffer each time a PE sees amarker indicating an end of a row, which is supplied by the DMU 1205. Inthis way, each PE produces a sum for the row sub-block it is responsiblefor. To produce the final sum for the row, the sub-block sums producedby all the PEs are added together by the Reduction Unit 1704 in the DMU(see FIG. 17). The final sums are written to the output buffer1713-1714, which the DMU 1005 then writes to memory.

Graph Data Processing

In one implementation, the accelerator architectures described hereinare configured to process graph data. Graph analytics relies on graphalgorithms to extract knowledge about the relationship among datarepresented as graphs. The proliferation of graph data (from sourcessuch as social media) has led to strong demand for and wide use of graphanalytics. As such, being able to do graph analytics as efficient aspossible is of critical importance.

To address this need, one implementation automatically maps auser-defined graph algorithm to a hardware accelerator architecture“template” that is customized to the given input graph algorithm. Theaccelerator may comprise the architectures described above and may beimplemented as a FPGA/ASIC, which can execute with extreme efficiency.In summary, one implementation includes:

(1) a hardware accelerator architecture template that is based on ageneralized sparse matrix vector multiply (GSPMV) accelerator. Itsupports arbitrary graph algorithm because it has been shown that graphalgorithm can be formulated as matrix operations.

(2) an automatic approach to map and tune a widely-used “vertex centric”graph programming abstraction to the architecture template.

There are existing sparse matrix multiply hardware accelerators, butthey do not support customizability to allow mapping of graphalgorithms.

One implementation of the design framework operates as follows.

(1) A user specifies a graph algorithm as “vertex programs” followingvertex-centric graph programming abstraction. This abstraction is chosenas an example here due to its popularity. A vertex program does notexpose hardware details, so users without hardware expertise (e.g., datascientists) can create it.

(2) Along with the graph algorithm in (1), one implementation of theframework accepts the following inputs:

a. The parameters of the target hardware accelerator to be generated(e.g., max amount of on-chip RAMs). These parameters may be provided bya user, or obtained from an existing library of known parameters whentargeting an existing system (e.g., a particular FPGA board).

b. Design optimization objectives (e.g., max performance, min area)

c. The properties of the target graph data (e.g., type of graph) or thegraph data itself. This is optional, and is used to aid in automatictuning.

(3) Given above inputs, one implementation of the framework performsauto-tuning to determine the set of customizations to apply to thehardware template to optimize for the input graph algorithm, map theseparameters onto the architecture template to produce an acceleratorinstance in synthesizable RTL, and conduct functional and performancevalidation of the generated RTL against the functional and performancesoftware models derived from the input graph algorithm specification.

In one implementation, the accelerator architecture described above isextended to support execution of vertex programs by (1) making it acustomizable hardware template and (2) supporting the functionalitiesneeded by vertex program. Based on this template, a design framework isdescribed to map a user-supplied vertex program to the hardware templateto produce a synthesizable RTL (e.g., Verilog) implementation instanceoptimized for the vertex program. The framework also performs automaticvalidation and tuning to ensure the produced RTL is correct andoptimized. There are multiple use cases for this framework. For example,the produced synthesizable RTL can be deployed in an FPGA platform(e.g., Xeon-FPGA) to efficiently execute the given vertex program. Or,it can be refined further to produce an ASIC implementation.

It is has been shown that graphs can be represented as adjacencymatrices, and graph processing can be formulated as sparse matrixoperations. FIGS. 19a-b shows an example of representing a graph as anadjacency matrix. Each non-zero in the matrix represents an edge amongtwo nodes in the graph. For example, a 1 in row 0 column 2 represents anedge from node A to C.

One of the most popular models for describing computations on graph datais the vertex programming model. One implementation supports the vertexprogramming model variant from Graphmat software framework, whichformulates vertex programs as generalized sparse matrix vector multiply(GSPMV). As shown in FIG. 19c , a vertex program consists of the typesof data associated with edges/vertices in the graph (edata/vdata),messages sent across vertices in the graph (mdata), and temporary data(tdata) (illustrated in the top portion of program code); and statelessuser-defined compute functions using pre-defined APIs that read andupdate the graph data (as illustrated in the bottom portion of programcode).

FIG. 19d illustrates exemplary program code for executing a vertexprogram. Edge data is represented as an adjacency matrix A (as in FIG.19b ), vertex data as vector y, and messages as sparse vector x. FIG.19e shows the GSPMV formulation, where the multiply( ) and add( )operations in SPMV is generalized by user-defined PROCESS_MSG( ) andREDUCE( ).

One observation here is that the GSPMV variant needed to execute vertexprogram performs a column-oriented multiplication of sparse matrix A(i.e., adjacency matrix) against a sparse vector x (i.e., messages) toproduce an output vector y (i.e., vertex data). This operation isreferred to as col_spMspV (previously described with respect to theabove accelerator).

Design Framework.

One implementation of the framework is shown in FIG. 20 which includes atemplate mapping component 2011, a validation component 2012 and anautomatic tuning component 2013. Its inputs are a user-specified vertexprogram 2001, design optimization objectives 2003 (e.g., maxperformance, min area), and target hardware design constraints 2002(e.g., maximum amount of on-chip RAMs, memory interface width). As anoptional input to aid automatic-tuning, the framework also accepts graphdata properties 2004 (e.g., type=natural graph) or a sample graph data.

Given these inputs, the template mapping component 2011 of the frameworkmaps the input vertex program to a hardware accelerator architecturetemplate, and produces an RTL implementation 2005 of the acceleratorinstance optimized for executing the vertex program 2001. The automatictuning component 2013 performs automatic tuning 2013 to optimize thegenerated RTL for the given design objectives, while meeting thehardware design constraints. Furthermore, the validation component 2012automatically validates the generated RTL against functional andperformance models derived from the inputs. Validation test benches 2006and tuning reports 2007 are produced along with the RTL.

Generalized Sparse Matrix Vector Multiply (GSPMV) Hardware ArchitectureTemplate

One implementation of an architecture template for GSPMV is shown inFIG. 21, which is based on the accelerator architecture described above(see, e.g., FIG. 17 and associated text). Many of the componentsillustrated in FIG. 21 are customizable (as highlighted with greylines). In one implementation, the architecture to support execution ofvertex programs has been extended as follows.

Customizable logic blocks are provided inside each PE to supportPROCESS_MSG( ) 1910, REDUCE( ) 2111, APPLY 2112, and SEND_MSG( ) 2113needed by the vertex program. In addition, one implementation providescustomizable on-chip storage structures and pack/unpack logic 2105 tosupport user-defined graph data (i.e., vdata, edata, mdata, tdata). Thedata management unit 1205 illustrated in FIG. 21 includes a PE scheduler1701 (for scheduling PEs as described above), aux buffers 2101 forstoring active column, x data), a read buffer 1702, a memory controller2103 for controlling access to system memory, and a write buffer 1704.In addition, in the implementation shown in FIG. 21 old and new vdataand tdata is stored within the local PE memory 1721. Various controlstate machines may be modified to support executing vertex programs,abiding to the functionalities specified by the algorithms in FIGS. 19dand 19 e.

The operation of each accelerator tile is summarized in FIG. 22. At2201, the y vector (vdata) is loaded to the PE RAM 1721. At 2202, the xvector and column pointers are loaded to the aux buffer 2101. At 2203,for each x vector element, the A column is streamed in (edata) and thePEs execute PROC_MSG( ) 2110 and REDUCE( ) 2111. At 2204, the PEsexecute APPLY( ) 2112. At 2205, the PEs execute SEND_MSG( ) 2113,producing messages, and the data management unit 1205 writes them as xvectors in memory. At 2206, the data management unit 1205 writes theupdated y vectors (vdata) stored in the PE RAMs 1721 back to memory. Theabove techniques conform to the vertex program execution algorithm shownin FIGS. 19d and 19e . To scale up performance, the architecture allowsincreasing the number of PEs in a tile and/or the number of tiles in thedesign. This way, the architecture can take advantage of multiple levelsof parallelisms in the graph (i.e., across subgraphs (across blocks ofadjacency matrix) or within each subgraph). The Table in FIG. 23asummarizes the customizable parameters of one implementation of thetemplate. It is also possible to assign asymmetric parameters acrosstiles for optimization (e.g., one tile with more PEs than another tile).

Automatic Mapping, Validation, and Tuning

Tuning.

Based on the inputs, one implementation of the framework performsautomatic tuning to determine the best design parameters to use tocustomize the hardware architecture template in order to optimize it forthe input vertex program and (optionally) graph data. There are manytuning considerations, which are summarized in the table in FIG. 23b .As illustrated, these include locality of data, graph data sizes, graphcompute functions, graph data structure, graph data access attributes,graph data types, and graph data patterns.

Template Mapping.

In this phase, the framework takes the template parameters determined bythe tuning phase, and produces an accelerator instance by “filling” inthe customizable portions of the template. The user-defined computefunctions (e.g., FIG. 19c ) may be mapped from the input specificationto the appropriate PE compute blocks using existing High-Level Synthesis(HLS) tools. The storage structures (e.g., RAMs, buffers, cache) andmemory interfaces are instantiated using their corresponding designparameters. The pack/unpack logic may automatically be generated fromthe data type specifications (e.g., FIG. 19a ). Parts of the controlfinite state machines (FSMs) are also generated based on the provideddesign parameters (e.g., PE scheduling schemes).

Validation.

In one implementation, the accelerator architecture instance(synthesizable RTL) produced by the template mapping is thenautomatically validated. To do this, one implementation of the frameworkderives a functional model of the vertex program to be used as the“golden” reference. Test benches are generated to compare the executionof this golden reference against simulations of the RTL implementationof the architecture instance. The framework also performs performancevalidation by comparing RTL simulations against analytical performancemodel and cycle-accurate software simulator. It reports runtimebreakdown and pinpoint the bottlenecks of the design that affectperformance.

One embodiment of a method is illustrated in FIG. 24. The method may beimplemented on the processor and system architectures described abovebut is not limited to any particular architecture.

At 2401, input graph program code and parameters associated with thetarget accelerator are received (e.g., the amount of on-chip memory,etc). In addition, at this stage design optimization objectives may alsobe received such as a maximum performance level and/or minimum siliconarea for the target accelerator. At 2402, the input graph program codeand parameters are analyzed in view of an accelerator architecturetemplate. For example, the accelerator architecture template maycomprise customizable logic blocks usable to generate the hardwaredescription representation (e.g., logic blocks defining on-chip storagestructures and pack/unpack logic to support user-defined graph data). At2403 parameters are mapped onto the architecture template to implementthe customizations. The customizations may also be applied usingparameters based on the design optimization objectives. As discussedabove, the mapping of parameters modifies the architecture template inaccordance with implementation-specific requirements. As illustrated inFIG. 21, parameters may be mapped to various components within theaccelerator architecture template including within the data managementunit 1205, processing element, and on-chip memory 1721 (as highlightedby diagonal lines). At 2404, a hardware description representation isgenerated for the target accelerator based on the mapping of theparameters to customize the accelerator architecture template. Forexample, in one embodiment, the hardware description representationcomprises RTL code as discussed above.

Embodiments of the invention may include various steps, which have beendescribed above. The steps may be embodied in machine-executableinstructions which may be used to cause a general-purpose orspecial-purpose processor to perform the steps. Alternatively, thesesteps may be performed by specific hardware components that containhardwired logic for performing the steps, or by any combination ofprogrammed computer components and custom hardware components.

In the foregoing specification, the embodiments of invention have beendescribed with reference to specific exemplary embodiments thereof. Itwill, however, be evident that various modifications and changes may bemade thereto without departing from the broader spirit and scope of theinvention as set forth in the appended claims. The specification anddrawings are, accordingly, to be regarded in an illustrative rather thana restrictive sense.

As described herein, instructions may refer to specific configurationsof hardware such as application specific integrated circuits (ASICs)configured to perform certain operations or having a predeterminedfunctionality or software instructions stored in memory embodied in anon-transitory computer readable medium. Thus, the techniques shown inthe Figures can be implemented using code and data stored and executedon one or more electronic devices (e.g., an end station, a networkelement, etc.). Such electronic devices store and communicate(internally and/or with other electronic devices over a network) codeand data using computer machine-readable media, such as non-transitorycomputer machine-readable storage media (e.g., magnetic disks; opticaldisks; random access memory; read only memory; flash memory devices;phase-change memory) and transitory computer machine-readablecommunication media (e.g., electrical, optical, acoustical or other formof propagated signals—such as carrier waves, infrared signals, digitalsignals, etc.). In addition, such electronic devices typically include aset of one or more processors coupled to one or more other components,such as one or more storage devices (non-transitory machine-readablestorage media), user input/output devices (e.g., a keyboard, atouchscreen, and/or a display), and network connections. The coupling ofthe set of processors and other components is typically through one ormore busses and bridges (also termed as bus controllers). The storagedevice and signals carrying the network traffic respectively representone or more machine-readable storage media and machine-readablecommunication media. Thus, the storage device of a given electronicdevice typically stores code and/or data for execution on the set of oneor more processors of that electronic device. Of course, one or moreparts of an embodiment of the invention may be implemented usingdifferent combinations of software, firmware, and/or hardware.Throughout this detailed description, for the purposes of explanation,numerous specific details were set forth in order to provide a thoroughunderstanding of the present invention. It will be apparent, however, toone skilled in the art that the invention may be practiced without someof these specific details. In certain instances, well known structuresand functions were not described in elaborate detail in order to avoidobscuring the subject matter of the present invention. Accordingly, thescope and spirit of the invention should be judged in terms of theclaims which follow.

What is claimed is:
 1. A non-transitory machine-readable medium havingprogram code stored thereon which, when executed by a processor, causesthe processor to perform the operations of: analyzing input graphprogram code and parameters associated with a target accelerator in viewof an accelerator architecture template; responsively mapping theparameters onto the architecture template to implement customizations tothe accelerator architecture template; and generating a hardwaredescription representation of the target accelerator based on thedetermined mapping of the parameters to apply to the acceleratorarchitecture template.
 2. The machine-readable medium as in claim 1wherein the hardware description representation comprises synthesizableregister-transfer level (RTL) code.
 3. The machine-readable medium as inclaim 1 wherein at least one of the parameters comprises a maximumamount of on-chip memory for the target accelerator.
 4. Themachine-readable medium as in claim 1 further comprising program code tocause the machine to perform the operations of: analyzing designoptimization objectives associated with the target accelerator anddetermining the set of customizations, in part, based on the designoptimization objectives.
 5. The machine-readable medium as in claim 4wherein the design optimization objectives include a maximum performancelevel and/or a minimum silicon area for the target accelerator.
 6. Themachine-readable medium as in claim 1 further comprising program code tocause the machine to perform the operations of: analyzing designoptimization objectives associated with the target accelerator anddetermining the set of customizations, in part, based on the designoptimization objectives.
 7. The machine-readable medium as in claim 1wherein the input graph program code comprises a vertex-centric graphprogramming abstraction.
 8. The machine-readable medium as in claim 1wherein the program code is to cause the machine to perform theadditional operations of: validating function and performance of thegenerated hardware description representation.
 9. The machine-readablemedium as in claim 4 wherein the program code is to cause the machine toperform the additional operations of: performing automatic tuning tooptimize the generated hardware description representation based on thedesign optimization objectives.
 10. The machine-readable medium as inclaim 9 wherein automatic tuning is performed based on tuningconsiderations including locality of data, graph data sizes, graphcompute functions, graph data structure, graph data access attributes,graph data types, and/or graph data patterns.
 11. The machine-readablemedium as in claim 1 wherein the accelerator architecture templatecomprises customizable logic blocks usable to generate the hardwaredescription representation.
 12. The machine-readable medium as in claim11 wherein the customizable logic blocks define functional units withina plurality of processing elements of the target accelerator.
 13. Themachine-readable medium as in claim 12 wherein the functional unitscomprise a first functional unit to receive messages to other processingelements, a second functional unit to support reduction operations, athird functional unit to execute a specified sequent of operations ondata, and a fourth functional unit to send messages to other processingelements.
 14. The machine-readable medium as in claim 12 wherein thecustomizable logic blocks define on-chip storage structures andpack/unpack logic to support user-defined graph data.
 15. A methodcomprising: analyzing input graph program code and parameters associatedwith a target accelerator in view of an accelerator architecturetemplate; responsively mapping the parameters onto the architecturetemplate to implement customizations to the accelerator architecturetemplate; and generating a hardware description representation of thetarget accelerator based on the determined mapping of the parameters toapply to the accelerator architecture template.
 16. The method as inclaim 15 wherein the hardware description representation comprisessynthesizable register-transfer level (RTL) code.
 17. The method as inclaim 15 wherein at least one of the parameters comprises a maximumamount of on-chip memory for the target accelerator.
 18. The method asin claim 15 further comprising: analyzing design optimization objectivesassociated with the target accelerator and determining the set ofcustomizations, in part, based on the design optimization objectives.19. The method as in claim 18 wherein the design optimization objectivesinclude a maximum performance level and/or a minimum silicon area forthe target accelerator.
 20. The method as in claim 15 furthercomprising: analyzing design optimization objectives associated with thetarget accelerator and determining the set of customizations, in part,based on the design optimization objectives.
 21. The method as in claim15 wherein the input graph program code comprises a vertex-centric graphprogramming abstraction.
 22. An apparatus comprising: a memory forstoring program code and data; a processor for executing the programcode and processing the data to perform the operations of: analyzinginput graph program code and parameters associated with a targetaccelerator in view of an accelerator architecture template;responsively mapping the parameters onto the architecture template toimplement customizations to the accelerator architecture template; andgenerating a hardware description representation of the targetaccelerator based on the determined mapping of the parameters to applyto the accelerator architecture template.
 23. The apparatus as in claim22 wherein the hardware description representation comprisessynthesizable register-transfer level (RTL) code.